The present disclosure relates generally to semiconductor device manufacturing, and more particularly, to dual strained channel semiconductor devices and methods for making the same.
Integrating NMOS and PMOS devices along with trench isolation where the end result is biaxially, tensile, strained Si used for NMOS channel and biaxially compressed SiGe used for PMOS channel is challenging. Typically, the starting material has either strained Si or compressed SiGe, and so enhancement of NMOS or PMOS takes place separately. Furthermore, the trench isolation module includes high temperature steps that can be detrimental to the degree of tensive or compressive strain in the respective channels.
Prior methods are known for enhancing performance for either PMOS or NMOS alone, but no known methods address simultaneous enhancement for both NMOS and PMOS devices, except for excessively high tensile strain. In one dual channel approach, a SiGe buffer layer is used; however, such an approach is not a dual channel solution for silicon on insulator (SOI). In another approach, wafer bonding is required to achieve tensile and compressive channels on a substrate.
Accordingly, it would be desirable to provide an improved semiconductor device manufacturing method for overcoming the problems in the art.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve an understanding of the embodiments of the present disclosure.